Paging & Page Tables
Paging is the mechanism that makes virtual memory work. It divides both virtual and physical memory into fixed-size chunks (pages), and maintains a translation table that maps virtual pages to physical ones.
Pages — 4KB Chunks
Page Tables — The Translation Map
x86-64 uses four-level page tables. A virtual address is split into five parts, each indexing into the next level of the table:
Each process has its own PGD (top-level page table). CR3 register points to the current process's PGD. On context switch, CR3 is updated, instantly switching to the new process's address space.
The TLB — Translation Lookaside Buffer
Context switches flush the TLB (or use Process Context IDs to avoid flushing). This is part of why context switching has overhead.
Page Faults — Three Types
| Type | Cause | Action | Cost |
|---|---|---|---|
| Minor | Page in RAM but not mapped in page table yet (e.g., after fork() CoW) | Update page table entry | Very fast — no disk I/O |
| Major | Page not in RAM — must read from disk (swap or mmap'd file) | Find page on disk, read into RAM, update table | Slow — disk latency (milliseconds) |
| Segfault | Access to unmapped or protected address | Send SIGSEGV to process | Process may die |
Frequently Asked Questions
What will I learn here?
This page covers the core concepts and techniques you need to understand the topic and progress confidently to the next lesson.
How should I use this page?
Start with the overview, then follow the section links to deepen your understanding. Use the table of contents on the right to jump to specific sections.
What should I read next?
Use the navigation below to continue to the next lesson or explore related topics.